# Flip-flops

## What do you need to know to understand this topic?

• Basics of digital logic

## What is a Flip-flop?

A Flip-flop (FF) is an electronic circuit that stores digital information, i.e., a single bit, when a specific type of edge (rising or falling) of a clock signal is detected. The pins of a FF are divided in 3 parts:

• Inputs - one or more inputs containing the data to be stored
• Clock - a specific edge (rising or falling) triggers the storage of the information
• Outputs - one output (and maybe its complement) that depends on the inputs and optionally on the current state
The following figure shows the signal relations of a general flip-flop that transfers the input bit to the output during a rising edge of the clock signal. Note that the output signal does not change when the input does, but only when the clock signal is asserted. Together with latches, they are the basic data storage element of synchronous logic, i.e., logic that changes the signal at times synchronized by a clock signal.

### What is the difference between Flip-flops and latches?

The main difference between flip-flops and latches is that latches are asynchronous while flip-flops are synchronous. A latch becomes "transparent" while the input clock is high. In this state, a change in its inputs takes immediate effect at its output. When the input clock is low, the output of the latch does not change. In latches, the clock is also known as Enable. The most simple latches are transparent all the time. On the other hand, a flip-flop takes a snapshot of its inputs only when a transition of the input clock occurs. Some examples of latches and their signals:

#### SR Latch (NOR type always transparent) SR Latch with two NORs Timing diagram of SR Latch

StateSRQ
hold 00$Q_{prev}$
reset 010
set 101
not allowed11???

Truth table of SR Latch

#### Gated SR Latch (transparent when E=1) SR Latch with enable Timing diagram of SR Latch with enable

StateSREQ
hold XX0$Q_{prev}$
hold 001$Q_{prev}$
reset 0110
set 1011
not allowed111???

Truth table of Gated SR Latch

## Types of Flip-flops

There are 3 types of flip-flops:

### Flip-flop D

The flip-flop type D (from Data) is the most widely used flip-flop. During a rising edge of the clock, its input $D$ is tranferred to the flip-flop's output $Q$. The output $\overline{Q}$ is always the complement of $Q$. The symbol and truth table of this flip-flop are shown below. StateDCLKQQ
no clockXnot rising edge$Q_{prev}$$\overline{Q}_{prev} reset0rising edge01 set1rising edge10 Any flip-flop can be designed to capture the input only at the falling edge of the clock instead. It is much more common, though, to design them to be triggered at the rising edge. ### Flip-flop T The flip-flop T gets its name from the fact that, during a rising clock edge, it toggles the output if its input T is high, and keeps the output unchanged if its input is low. The symbol and truth table of this flip-flop are shown below. StateTCLKQQ no clockXnot rising edgeQ_{prev}$$\overline{Q}_{prev}$
hold0rising edge$Q_{prev}$$\overline{Q}_{prev} toggle1rising edge\overline{Q}_{prev}$$Q_{prev}$

Looking at the truth table, we can see that this flip-flop can be compactly described by the characteristic equation: $$Q=T\overline{Q}_{prev} + \overline{T}Q_{prev}$$ You may be asking how is the output defined in the first place. It may be that is does not matter: if this flip-flop toggles the output at each rising edge of the input clock, the output is also a clock with half the period of the input clock. It then works as a clock divider and it doesn't really matter how it started in the first place. If the initial output matters, any flip-flop can be equipped with asynchronous set or reset, that is, inputs that set or reset the output independently of the clock signal.

### Flip-flop JK

The Flip-flip JK combines the functionalty of flip-flops D and T, because it can set/reset and hold/toggle the output. The symbol and truth table of this flip-flop are shown below. When $J = K$, they can be used to keep or toggle the output. When they are different, $Q$ follows $J$ and $\overline{Q}$ follows $K$. In that sense, the flip-flop D is a particular case of this one, when $K$ is always the complement of $J$ and the flip-flop T is another particular case, when $J$ and $K$ are connected together. StateJKCLKQ
no clockXXnot rising edge$Q_{prev}$
hold00rising edge$Q_{prev}$
reset01rising edge0
set10rising edge1
toggle11rising edge$\overline{Q}_{prev}$

Looking at the truth table, we can see that this flip-flop can be compactly described by the characteristic equation: $$Q = J\overline{Q}_{prev} + \overline{K}Q_{prev}$$

## Clock to Queue, Setup and Hold times

It seems that the way flip-flops work is pretty simple and not much problems can come from them. However, things get complicated when the period of the clock signal is of the same order of magnitude as the timings of the flip-flop itself.

The example circuit below is made of two flip-flops synchronized by the same clock clk and with some combinatorial logic in between. Each of these flip-flops has the following properties:

• Clock to Queue or Clock to Output $t_{ckq}$: The time the flip-flop takes to change its output after a (rising) clock edge
• Setup time $t_{s}$: the time during which the input must not change before a (rising) clock edge
• Hold time $t_{h}$: the time during which the input must not change after a (rising) clock edge

The setup and hold time combined define a band around the edge of a clock in which the input signal of the flip-flop cannot change. The idea is that a flip-flop needs some time to setup before the edge of the clock and some time after the clock to hold the input signal. If this is not guaranteed, neither is the output of the flip-flop after the clock edge. Both times vary strongly with process, voltage and temperature (PVT). The combinatorial logic also has its own propagation delay $t_d$, which means that i2 is delayed with respect to o1. Circuit used to show flip-flop timing requirements

To help us undestand how these timing properties constrain the synchronous logic, the interactive plot below lets you configure the clock period, the hold/setup and clock to queue times of the flip-flops (we assume they are equal) and the propagation delay of the combinatorial circuit.

Now, lets take it in parts, like Jack the Ripper. You can see the left and right red bands around each rising edge of the clock, representing the setup and hold times. After each clock edge, the gray band represents the clock to queue period. After this period, you see the change in o1. After that, the blue band represents the propagation delay of the combinatorial circuit. At the end of this band, the input of FF2 changes. So, the next clock edge must be at least one setup time after the end of this band. The extra time above this lower bound $t_{ss}$ is called setup time slack. If the delay of the combinatorial logic and/or the clock to queue time is increased, the FF2 will end up violating its setup time. If they are decreased, i2 may change too soon, violating the hold time of FF2. As in the setup, the slack between the end of the hold band and the input change is called hold time slack. So, for the same clock period, there is a compromise between setup and hold time slacks. Play around and see when the setup and hold band are violated, making the bands live red.

Clock to Queue
Propagation delay
Setup/hold times
Violation of Setup/hold times

ParameterSymbolValueSlider
Clock period$t_{clk}$
Clock to Queue$t_{ckq}$
Propagation Delay$t_d$
Required Setup time$t_s$
Required Hold time$t_h$

What we see from the experiment is that the clock period $t_{clk}$ must be larger than $t_{ckq} + t_d + t_s$. Whatever time remains is the setup time slack: $$t_{ss} = \textrm{(setup time available) - (setup time required)} = (t_{clk} - t_{ckq} - t_d) - t_s$$

Regarding the hold time slack, we can see that when FF1 and FF2 are triggered, the input of FF2 stays steady for $t_{ckq} + t_{d}$. This is the available hold time. The hold time slack is: $$t_{hs} = \textrm{(hold time available) - (hold time required)} = (t_{ckq} + t_{d}) - t_h$$ The worst case scenario is when two flip-flops are connected one next to the other (no combinatorial logic in between), which makes $t_d = 0$. That case imposes the design constraint $t_{ckq} > t_h$.

### Clock skew

There is another aggravation, this time related to the clock. The clock signal may take a different route to each flip-flop, each one with a different propagation delay. This causes the clock edge to arrive at different times for each flip-flop. This mismatch $\Delta t$ is known as clock skew. In the example below, say $\Delta t > 0$ when clock arrives later at FF2 than at FF1 and $\Delta t < 0$ otherwise. The signals diagram below is different from the first because clk1 and clk2 are no longer aligned. The slider for parameter clock skew lets you control the amount of disalignment between the clocks reaching both flip-flops. The clock arriving at FF2 (clk2) is delayed (positive clock skew) or advanced (negative clock skew) in comparison to the clock arriving at FF1 (clk1). By playing around with the clock skew, you will soon realize that a clock in FF2 in advance of the clock in FF1 injures the setup time slack of FF2, while a delayed clock in FF2 injured its hold time slack.

Clock to Queue
Propagation delay
Setup/hold times
Violation of Setup/hold times

ParameterSymbolValueSlider
Clock period$t_{clk}$
Clock skew$t_{cs}$
Clock to Queue$t_{ckq}$
Propagation Delay$t_d$
Required Setup time$t_s$
Required Hold time$t_h$

In other words, the clock skew, defined here as the difference of clock arrival between FF2 and FF1, adds to the setup time slack and substracts to the hold time slack. Accounting with clock skew, we get the following slack times: $$t_{ss} = t_{clk} - t_{ckq} - t_d - t_s + t_{cks}$$ $$t_{hs} = t_{ckq} + t_{d} - t_h - t_{cks}$$ The clock skew gives to one slack what takes from the other. If we slow down the clock (increasing its period), we can increase the setup time slack. However, there is no way the hold time slack can be changed without changing the design.

## Metastability

What happens when the input changes close enough to the clock edge so that it violates the setup or hold times? It happens a condition known as metastability, where the flip-flop cannot decide what input changed first and its output lingers in an undefined state for a while, until it settles in a certain state. Since there is not a bounded time for the flip-flop to decide on the result, the circuit that uses the result can get garbage in the next clock edge (assuming it is another synchronized block).

When the input is synchronized with the clock (as in FF2 in the examples above), we have the knowledge of when it can change and proper design can guarantee that metastability never happens. However, it is common to have flip-flops that capture an input that is unrelated to the clock signal and the edges of both clock and input can be arbitrarily close together. Therefore, there is no way to avoid entirely the metastability problem in such cases. A common solution is to chain two or more flip-flops synchronized by the same clock. This will increase the time the first flip-flop has to leave metastability, since only after $N$ clock cycles (with $N + 1$ chained flip-flops) will the last flip-flop capture the change in the input of the first flip-flop. The more flip-flops you chain, the more time metastability is allowed and the more robust the circuit is. So, the solution just reduces the probability of metastability, but it never eliminates it.

## Flip-flop design

For IC designers, this section goes in depth about flip-flop design. There are a lot of design approaches, so we will go through some diverse options. We will focus on the flip-flop D, although similar considerations can be made to other flip-flops.

### Dynamic master-slave flip-flop D  This is a very simple to understand flip-flop. It is called dynamic because in some situations the nodes are floating and the charge is stored in the node's capacitance. As a result, if the clock does not change frequently enough, the node may discharge due to transistor leakage and the state may change. You may recognize each stage of this flip-flop as a dynamic latch D, gated by the clock signal. It is also called master-slave because the second latch in the series only changes in response to a change in the first (master) latch. When clk is low, the first stage captures the input D. When the clock is asserted, the intermediate node is transferred to the output. During the clock transitions and due to the inverter delay (the one that inverts the clock signal), for brief moments both clk and its complement have the same value. Is this a problem? From the above figure, we can see that it is not. The left situation is when the second latch is becoming transparent, while the first one is losing transparency. During this period, only the the pull-down transistors are active. The right situation is when the first latch is becoming transparent, while the second one is losing transparency. In this case, only the pull-up transistors are active. Both represent a similar situation: if input D is able to drive the middle node a (e.g. D=1 in the left example or D=0 in the right example), that node will not be able to drive the output node. If the examples are switched (D=0 in the left example or D=1 in the right example), not even the internal node can be driven. Therefore, the output does not change either way. Only a combination of pull-up and pull-down stages could change the output. This could eventually happen if the clock rise/fall times (clock slew) were too slow. However, it is easy to design the clocks to rise or fall faster than the propagation delay of the flip-flop.

### Static master-slave flip-flop D This flip-flop is similar to the previous design because it is also made of two type D latches. However, it is static because both latches are static in the sense that the nodes are always being driven. When clk is low, the first stage captures the input D, while the second stage has two cross-coupled inverters to keep regenerating the output nodes. When the clock is asserted, the intermediate node is transferred to the output and the nodes of the first stage are regenerated by another two cross-coupled inverters. The main problem with this design is that overlap of clk and its complement will:

• open node a to nodes D and b simultaneously, potentially setting node a to an undefined value
• create a direct path from the input to the output during both clock edges Even if the clocks had exact timing by design, clock skew and clock slew (rise/fall times) would always generate a certain overlap. The solution to this problem is to have two non-overlapping clocks, even accounting with all possible clock skew and slew. In this case, a significant portion of time both clocks are off, which leaves the internal nodes floating. For this reason, this is called a pseudostatic flip-flop.

### Positive-edge triggered dynamic D flip-flop This flip-flop is also called dynamic for the same reason as the first one. The advantage of this type of flip-flops is the high speed and low-power consumption. Unlike the first one, it is not made of two latches. Instead, it follows a complicated logic that depends on its two internal nodes a and b.

To follow the state of this flip-flop, we need to keep track of the transitions of its inputs and also its previous state. There are only two conditions, both when clock is low, that set the internal states of this flip-flop into known values, shown in the left truth-table. In these conditions, the output keeps its previous value. When the clock rises, some internal states keep unchanged while others change, leading to an output that captures the input (shown in the middle truth table). Finally, with clock high, if the inputs change, the node b stays steady, which in turn does not change the output (shown in the right truth table). When the clock goes low again, we go back to one of the first two conditions, which do not change the output.

DCLKabQ CLK rises DCLKabQ D switches DCLKabQ
00 11$\overline{Q}_{prev}$ 01 $a_{prev}$=101 11 0$b_{prev}$=01
10 01$\overline{Q}_{prev}$ 11 0$b_{prev}$=10 01 $a_{prev}$=0$b_{prev}$=10

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