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# The MOSFET Model

## Regions of operation

The MOSFET operation was demonstrated in another topic, but in order to do any kind of analysis or simulation, it is required a model that represents the behavior of the transistor.

Symbols of the NMOS and PMOS transistors

The MOS structure

Depending on the bias conditions of the transistor (the voltages applied to it), the transistor can be at different regions of operation, that are distinct in the way currents and voltages interplay.

### Triode region

For $V_{DS} \lt V_{GS} - V_{TH}$, we expect that the drain current increases with $V_{GS}$ because it increases the channel conductivity and also with $V_{DS}$ because it is the voltage across the channel. The relation is defined as $$$$I_{DS} = \mu C_{ox}\frac{W}{L}\left((V_{GS}-V_{TH})V_{DS} - \frac{1}{2}V_{DS}^2 \right)\label{eq:triode}$$$$ where $\mu$ is the mobility of the electric carrier (electrons for NMOS $\mu_n$ and holes for PMOS $\mu_p$), $C_{ox}$ is the oxide capacitance and $W$ and $L$ are the transistor's width and length. The drain current is directly proportional to $V_{GS}$ as expected and it has a non-linear dependence with $V_{DS}$ because of the tapering of the channel.

I saved you the dirty details. If you want to find out how this equation is derived, click here.

The charge in the channel and in the gate terminal, together with the oxide isolator between them form a capacitor $C_{ox}$.

Due to the tapering of the channel, the voltage across this capacitor is not equal throughout the channel. Instead, the voltage across $C_{ox}$ at the source is $V_{GS} - V_{TH}$ and at the drain is $V_{GD} - V_{TH} = V_{GS} - V_{TH} - V_{DS}$ (note that only when $V_{GS} > V_{TH}$ a channel is formed). In general, at point $x$ is: $$V_{C_{ox}}(x) = V_{GS} - V_{TH} - V(x)$$ where $V(0) = 0$ at the source and $V(L) = V_{DS}$ at the drain. At point $x$, the point charge is Q = CV: $$dQ(x) = -C_{ox}Wdx(V_{GS} - V_{TH} - V(x)).$$ $C_{ox}Wdx$ is just a slice of the capacitor at a infinitesimal $dx$ and $dQ(x)$ has negative sign because the charge is negative. The electric field created by the voltage difference at any $dx$ is: $$E(x) = -\frac{dV(x)}{dx}.$$ This electric field is in the opposite direction of the voltage difference and pushes the charge in the same direction as the voltage difference with velocity: $$\frac{dx}{dt} = -\mu E(x) = \mu\frac{dV(x)}{dx}$$ where $\mu$ is the mobility of the majority carriers (electrons for NMOS and holes for PMOS). Being the current the derivative of charge relative to time: $$I_{DS} = -\left(\frac{dQ(x)}{dx}\frac{dx}{dt}\right) = C_{ox}W(V_{GS} - V_{TH} - V(x))\mu\frac{dV(x)}{dx}$$ which can be rearranged to $$I_{DS}dx = \mu C_{ox}W(V_{GS} - V_{TH} - V(x))dV(x).$$ Now we take the integral on both sides, the left relative to $dx$, the right relative to $dV(x)$: $$\int_0^L{I_{DS}dx} = \int_0^{V_{DS}}{\mu C_{ox}W(V_{GS} - V_{TH} - V(x))dV(x)}.$$ $$I_{DS}L = \left [ \mu C_{ox}W\left((V_{GS} - V_{TH})V(x) - \frac{V(x)^2}{2} \right)\right]_0^{V_{DS}}.$$ $$I_{DS} = \mu C_{ox}\frac{W}{L}\left((V_{GS} - V_{TH})V_{DS} - \frac{V_{DS}^2}{2}\right).$$

### Saturation region

When the transistor reaches saturation, $V_{DS} = V_{GS}-V_{TH}$ and $\eqref{eq:triode}$ becomes $$I_{DS} = \mu C_{ox}\frac{W}{L}\left((V_{GS}-V_{TH})(V_{GS}-V_{TH}) - \frac{1}{2}(V_{GS}-V_{TH})^2 \right)$$ $$$$I_D = \frac{1}{2}\mu C_{ox}\frac{W}{L}\left(V_{GS}-V_{TH} \right)^2\label{eq:saturation}$$$$ This region is also referred as the square-law, since the drain current is proportional to the square of $V_{GS}$.

## Characteristic curves

It is often good to see the relationship between variables in a plot to have a better understanding of what is happening. The most important variables are the drain current $I_{DS}$, the gate-source voltage $V_{GS}$ and the drain-source voltage $V_{DS}$. The two voltages influence the drain current and thus is convenient to show the $I_{DS}-V_{GS}$ and $I_{DS}-V_{DS}$ plots. In the following plots, $V_{TH} = 0.5V$ and $\mu C_{ox}W/L = 1 mA/V^2$.

### The $I_{DS}-V_{GS}$ curve

It can be seen by this plot that for $V_{DS} \gt V_{GS} - V_{TH}$ (or $V_{GS} \lt V_{DS} + V_{TH}$), the transistor is in saturation and the curve bends due to the square law. For $V_{DS} \lt V_{GS} - V_{TH}$ (or $V_{GS} \gt V_{DS} + V_{TH}$), the relation $I_{DS}-V_{GS}$ becomes linear as it should be in the triode region.

### The $I_{DS}-V_{DS}$ curve

This plot shows that while $V_{GS} \lt V_{TH}$, no current flows through the channel. Furthermore, the non-linear relation between $I_{DS}$ and $V_{DS}$ in the triode region can also be seen, as well as the plateau the current reaches when the transistor enters in saturation. The dashed line separates the triode and the saturation regions and marks the points where $V_{DS} = V_{GS} - V_{TH}$.

Truth be told, the plateaus you see above are not completely flat. In saturation, there is some dependence between $I_{DS}$ and $V_{DS}$. In order to know why, you need to understand what is channel length modulation.

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