# MOS Transistor parasitic capacitances

## What are parasitic capaticances?

These are unwanted capacitances, but still are part of the transistor. Together with the resistances in the circuit, they put an upper limit to the speed of the transistor. First, let us see what kind of capacitances a transistor has.

## Types of parasitic capacitances $C_1$ and $C_2$ are capacitances created by the depletion regions between source/drain and bulk. $C_3$ is the depletion capacitance between the channel and bulk. $C_4$ and $C_5$ are capacitances caused by the overlap between the gate and the source/drain diffusions. Finally, $C_6$ is the oxide capacitance between gate and the channel and is split between drain and source depending on the region of operation of the transistor. We want to map this physical capacitances to the terminals of the transistor, so we can use them in our model.

### Junctions depletion capacitances

$C_1$ and $C_2$ are capacitances created by the depletion regions of the junctions between source/drain and bulk. These junctions are three-dimensional: 3 sides that are away from the channel, one side that is in front of the channel, and the bottom side (the upper side has isolator above it, so it has no depletion). We define 3 normalized capacitances
• $C_{ja}$ - Bottom plate capacitance per unit area ($fF/\mu m^2$)
• $C_{jp}$ - Sidewalls away from channel capacitance per unit length ($fF/\mu m$). The height is a process parameter and is included in the capacitance
• $C_{jpg}$ - Sidewall in front of the channel capacitance per unit length ($fF/\mu m$). The height is a process parameter and is included in the capacitance

In order to calculate $C_{SB}$ or $C_{DB}$, we need to sum all these capacitances. $$C_{SB} = C_{DB} = WEC_{ja} + (W + 2E)C_{jp} + WC_{jpg}$$

### Overlap and gate-channel capacitances

$C_4$ and $C_5$ are overlap capacitances and are only proportional to the width of the transistor. $C_6$ is the gate-channel capacitance and its total value is split between drain and source in a way that depends on the region of operation of the transistor.

First, we define the normalized capacitances:

• $C_{ov}$ - Overlap capacitance per unit length ($fF/\mu m$)
• $C_{ox}$ - Gate to channel capacitance per unit area ($fF/\mu m^2$)

$C_{GS}$ and $C_{GD}$ have a base value of the overlap capacitance $WC_{ov}$. To that we add the gate to channel capacitance $WL C_{ox}$ according to the region of operation: In subthreshold region, there is no gate-channel capacitance because there is no channel. In saturation, the channel is pinched-off and there is no gate-channel capacitance at the drain and only two-thirds go to the source. In triode, the channel is not pinched-off and the gate-channel capacitance is split equally between drain and source.

### Channel-bulk depletion capacitance

This capacitance is only relevant in subthreshold regime. In strong inversion, the channel is being driven and shields the transistor from this capacitance. However, in subthreshold there is no channel and this capacitance is in series with the oxide capacitance. Furthermore, $C_{GS}$ and $C_{DS}$ are made of only the overlap capacitance and they are small.

## High-frequency small-signal model

All these capacitances can be introduced into the low-frequency small-signal model to make it into a high-frequency small-signal model: The speed of a transistor can be measured by the unity-gain frequency $f_T$. It is the frequency at which the current that enters the gate $i_{in}$ equals the current that flows through the channel $i_{out}$. When in strong inversion and saturation, $C_{GS}$ is dominant with respect to $C_{GD}$ and $C_{GB}$ and these can be neglected. Then $$v_{gs} = \frac{i_{in}}{s(C_{GS}+ C_{DS} + C_{GB})} \approx \frac{i_{in}}{sC_{GS}}$$ $$i_{out} = g_m v_{gs} \approx g_m \frac{i_{in}}{sC_{GS}}$$ $$s \approx g_m \frac{i_{in}}{i_{out} C_{GS}} \approx \frac{g_m}{C_{GS}}$$ $$f_T \approx \frac{g_m}{2\pi C_{GS}}$$

## Summary

Parasitic capacitances of the MOS transistor can be incorporated into the small-signal model to make it valid at high-frequency operation. The following table summarizes the capacitances in the transistor:

Capacitance Off (subthreshold) Strong Inversion
Saturation Triode
$C_{GS}$ $$WC_{ov}$$ $$WC_{ov} + \frac{2}{3}WL C_{ox}$$ $$WC_{ov} + \frac{1}{2}WL C_{ox}$$
$C_{GD}$ $$WC_{ov}$$ $$WC_{ov}$$ $$WC_{ov} + \frac{1}{2}WL C_{ox}$$
$C_{GB}$ $$\frac{n-1}{n}WL C_{ox}$$ $$\approx 0$$
$C_{SB}/C_{DB}$ $$WE C_{ja} + (W + 2E)C_{jp} + WC_{jpg}$$

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