Source: http://onmyphd.com/?p=mosfet.model

- The MOSFET operation (it helps)
- Circuit theory

The MOSFET operation was demonstrated in another topic, but in order to do any kind of analysis or simulation, it is required a model that represents the behavior of the transistor.

Symbols of the NMOS and PMOS transistors

The MOS structure

Depending on the bias conditions of the transistor (the voltages applied to it), the transistor can be at different regions of operation, that are distinct in the way currents and voltages interplay.

For $V_{DS} \lt V_{GS} - V_{TH}$, we expect that the drain current increases with $V_{GS}$ because it increases the channel conductivity and also with $V_{DS}$ because it is the voltage across the channel. The relation is defined as $$\begin{equation}I_{DS} = \mu C_{ox}\frac{W}{L}\left((V_{GS}-V_{TH})V_{DS} - \frac{1}{2}V_{DS}^2 \right)\label{eq:triode}\end{equation}$$ where $\mu$ is the mobility of the electric carrier (electrons for NMOS $\mu_n$ and holes for PMOS $\mu_p$), $C_{ox}$ is the oxide capacitance and $W$ and $L$ are the transistor's width and length. The drain current is directly proportional to $V_{GS}$ as expected and it has a non-linear dependence with $V_{DS}$ because of the tapering of the channel.

I saved you the dirty details. If you want to find out how this equation is derived, click here.The charge in the channel and in the gate terminal, together with the oxide isolator between them form a capacitor $C_{ox}$.

When the transistor reaches saturation, $V_{DS} = V_{GS}-V_{TH}$ and $\eqref{eq:triode}$ becomes $$I_{DS} = \mu C_{ox}\frac{W}{L}\left((V_{GS}-V_{TH})(V_{GS}-V_{TH}) - \frac{1}{2}(V_{GS}-V_{TH})^2 \right)$$ $$\begin{equation}I_D = \frac{1}{2}\mu C_{ox}\frac{W}{L}\left(V_{GS}-V_{TH} \right)^2\label{eq:saturation}\end{equation}$$ This region is also referred as the square-law, since the drain current is proportional to the square of $V_{GS}$.

It is often good to see the relationship between variables in a plot to have a better understanding of what is happening. The most important variables are the drain current $I_{DS}$, the gate-source voltage $V_{GS}$ and the drain-source voltage $V_{DS}$. The two voltages influence the drain current and thus is convenient to show the $I_{DS}-V_{GS}$ and $I_{DS}-V_{DS}$ plots. In the following plots, $V_{TH} = 0.5V$ and $\mu C_{ox}W/L = 1 mA/V^2$.

It can be seen by this plot that for $V_{DS} \gt V_{GS} - V_{TH}$ (or $V_{GS} \lt V_{DS} + V_{TH}$), the transistor is in saturation and the curve bends due to the square law. For $V_{DS} \lt V_{GS} - V_{TH}$ (or $V_{GS} \gt V_{DS} + V_{TH}$), the relation $I_{DS}-V_{GS}$ becomes linear as it should be in the triode region.

This plot shows that while $V_{GS} \lt V_{TH}$, no current flows through the channel. Furthermore, the non-linear relation between $I_{DS}$ and $V_{DS}$ in the triode region can also be seen, as well as the plateau the current reaches when the transistor enters in saturation. The dashed line separates the triode and the saturation regions and marks the points where $V_{DS} = V_{GS} - V_{TH}$.

Truth be told, the plateaus you see above are not completely flat. In saturation, there is some dependence between $I_{DS}$ and $V_{DS}$. In order to know why, you need to understand what is channel length modulation.