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Switched-current analog memories

What do you need to know to understand this topic?

Sections

What is a switched-current memory?

The switched-current memory (for short SI memory) is a memory that stores an analog value represented by a current in a capacitor and uses the $I_D-V_{GS}$ relation of a MOS transistor to do the conversion between current and voltage. Suppose you have a diode-connected transistor and is collecting a current $I_{in}$. It develops a gate-source voltage according to

$$ I_{in} = \beta\left(V_{GS} - V_{TH}\right)^2 $$

where $\beta=1/2\mu_n C_{ox}W/L$. If the connection between gate and drain is broken, the charge in the gate has nowhere to go and remains constant. If now the transistor is working as a current source, it will produce the same current as it collected. The MOS transistor converted the current into voltage and stored it. Afterwards, it converts the gate voltage into the same current and supplies it.

Problems with switched-current memory

There are a few problems with the simple approach described above.
  1. The drain and gate must be connected by a switch. Real switches inject charge during switching into the gate that depends on the voltage at its terminals. That introduces an error in the stored charge.
  2. The drain current is lightly dependent on the drain-source voltage $V_{DS}$. During storage, $V_{DS}$ is equal to $V_{GS}$ (signal dependent), but during current supply it is unknown. Any difference in $V_{DS}$ between writing and reading the current will cause a difference between $I_{in}$ and $I_{out}$.

Class A S2I analog memory

To overcome some of these problems, in S2I the storage of current is done in two steps. In the first step, the current $I_{ref} + I_{in}$ is stored in an NMOS transistor, as before. In the second step, a PMOS transistor captures the current error $\Delta I$ caused by the charge injection in the NMOS gate and also by the change in $V_{DS}$. The PMOS also suffers from charge injection when the second step ends, but the error is much less signal dependent because it only depends on $\Delta I$, which is usually small. It is like we are capturing the signal and adding a part of it in the NMOS, and then we are capturing that part and adding a part of that in the PMOS. During the read of the current, both NMOS and PMOS supply their currents and the $I_{ref} + \Delta I$ term is cancelled by each other, leaving the term $I_{out} + \delta I$.

The complete circuit, including switches, is shown next.

So the benefits of using S2I cells is that the charge injection errors are reduced and $V_{DS}$ during the end of the second phase is very close to $V_{ref}$ whatever the signal $I_{in}$ may be. If the next stage follows the same procedure, the error caused by the output conductance is also very small.

Problems with S2I class A memories

There are still some problems with this S2I analog memory.

  1. Even if the input current is zero, this memory still consumes $I_{ref}$ during each write and read.
  2. The input current is limited to $I_{ref}$.
  3. As the input current changes, the transconductance of the PMOS transistor $g_{mp}$ is fixed, but the transconductance of the NMOS transistor $g_{mn}$ changes. During write, $g_{mn}$ and $g_{mp}$ make part of the input conductance, which makes the bandwidth of the memory signal dependent.

Class AB S2I analog memory

So the previous type of S2I memory is class A. That is because there is a constant supply of current. The class AB type uses a NMOS and PMOS composite to store current in each step.

During the first step, the composite of the left side stores the input current $I_{in}$ plus the current coming from the right side $I_{ref}$. $I_{ref}$ is the difference of currents coming from the PMOS and NMOS of the right side. At the end of the first step, a charge is injected when the gates and drains of the transistors in the left side are disconnected. The charge is injected to both transistors, but let us simplify by pushing all the charge injected to the NMOS. During the second step, the right side becomes diode-connected and stores $I_{in}$ plus the current stored previously on the left side. Due to charge injection, the current has an error term $\Delta I$. The current now stored in the right side is equal to the original term $I_{ref}$ plus the error term $\Delta I$. During read, both sides are supplying currents and the result is $I_{ref} + \delta I$, where $\delta I$ is the error term from the charge injected in the right side. All other terms are cancelled.

Advantages of class AB memories

The input current can be 4 times the quiescent current

The class A can only store $I_{in} > -I_{ref}$. In the limit condition of $I_{in} = -I_{ref}$, the NMOS has zero current. However, the class AB can store $ -4J \lt I_{in} \lt 4J$, where $J$ is the current flowing through the stacked NMOS and PMOS, if they were alone. Why is that? Consider that the transistors were sized such that they have the same overdrive voltage. Then $$ J = \frac{\beta_p}{2} \Delta V_{SG_p}^2 $$ $$ J = \frac{\beta_n}{2} \Delta V_{GS_n}^2 $$ For any input current, while one gate-source voltage increases, the other decreases, because the input current is being distributed by both transistors. The limit case is when one transistor is switched off ($\Delta V_{GS}$ or $\Delta V_{SG} = 0$) and the other doubled its overdrive voltage. To double the overdrive voltage is to drive 4x more current.

The bandwidth is signal independent

Suppose transistors are sized to have the same transconductance. $$g_{m_p} = \beta_p \Delta V_{SG}$$ $$g_{m_n} = \beta_n \Delta V_{GS}$$ For any input current, the changes in $\Delta V_{SG}$ or $\Delta V_{GS}$ are going to change the transconductance of each transistor by this linear relation. However, since when one increases, the other decreases accordingly, the total transconductance $G_m = g_{m_n} + g_{m_p}$ remains constant. Since transconductance is the input conductance during write, the bandwith is signal independent.

S3I or seamless S2I swiched-current

There is still another type of switched-current memory called S3I because it has added benefits compared to S2I, or called seamless S2I because it uses the same clock sequence.

Accurate analog memory

This memory is not based on making the charge injection signal independent, but instead aims to cancel charge injection altogether.

There are two capacitors that store the gate voltage of the memory transistor. When $S_2$ is turned off, clock feedthrough transfers a charge $\Delta Q$ from each terminal of the switch $S_2$. The charge is removed from $C_2$ because it is floating, while in $C_1$ is assimilated because $S_1$ is still on. When $S_1$ turns off, the same happens, and $\Delta Q$ is transferred from $C_1$. In the final step, when $S_2$ turns on, $\Delta Q$ is transferred to each side of $S_2$, cancelling the original loss.

Other enhancement techniques

Output switch compensation

During sampling, the drain node is forced to $V_{ref}$ by the PMOS that is receiving the same current it supplied ($I_{ref}$). During hold, the next stage forces its drain node to $V_{ref}$ the same way, but the output switch resistance has a voltage drop that sets the drain voltage of the hold memory to $V_{ref} - I_{in}r_s$. The memory has a different drain voltage between sample and hold and that causes an error due to channel length modulation.

One way to solve this is to add a resistance of the same value as the output switch between the input and the drain node. This can be a switch always turned on equal to the output switch . Then, a voltage $V_{ref}$ at the gate of the PMOS will lead to $V_{ref} - I_{in}r_s$ in the drain node. During hold, this resistance has no effect, and the same voltage will show up at the drain node.

Cancelling capactive coupling in differencial signal

The gate-drain capacitance of the memory transistors let charge be transferred between drain and gate through capactive coupling when the drain voltage changes. Differential circuits can use a technique that cancels the capacitive coupling by creating a counter capacitive coupling.

In the figure above, the drain node of one side affects the gates of the other side through capacitive coupling. Capacitances are sized such that $C_p = C_{gd_p}$ and $C_n = C_{gd_n}$. Why? Let's say that the drain voltage of the left side changes by $\Delta V_{ds}$. $C_{gd}$ coupling changes the gate voltage on the same side and that changes the current by $$ \Delta I_n = g_{m_n} \frac{C_{gd_n}}{C_{gd_n} + C_{g_n}} \Delta V_{ds}.$$ $$ \Delta I_p = g_{m_p} \frac{C_{gd_p}}{C_{gd_p} + C_{g_p}} \Delta V_{ds}.$$ However, the newly added capacitances $C_p$ and $C_n$ also change the current at the right side by $$ \Delta I_n = g_{m_n} \frac{C_n}{C_n + C_{g_n}} \Delta V_{ds}.$$ $$ \Delta I_p = g_{m_p} \frac{C_p}{C_p + C_{g_p}} \Delta V_{ds}.$$ If $C_p = C_{gd_p}$ and $C_n = C_{gd_n}$, the change of current is equal on both sides and the differential current remains the same. For convenience, the capacitances are made of the same transistors as the memory transistors to make the capacitances match more easily.

Drain-substrate capacitance discharge

This enhancement is not done to increase accuracy or reduce error, but instead it makes the memory settle faster. The problem in S2I memories is that during the coarse phase (when the NMOS is diode-connected) the drain-substrate capacitance $C_{db}$ is charged to some voltage $V_{db}$ that depends on the input current. At the beginning of the fine phase (when the PMOS is diode-connected) $C_{db}$ discharges to the gate of PMOS, developing a peak as shown below. The peak delays the settling, which in turn makes the memory slower than conventional SI memories.

To counter this effect, a switch controlled by a short pulse $\phi_d$ is connected to the common drain node and $V_{ref}$. At the beginning of step $\phi_{1b}$ this switch turns on for a short time to discharge $C_{db}$ quickly and then it turns off. This way, the peak is supressed and the memory settles faster.

Dummy switches

Dummy switches are used to cancel the clock-feedthrough of the already existing switches. As the name says, they really do not connect or disconnect part of the circuits, because their drain and source are connected together. They just inject or remove charge through their parasitic capacitances, when the effective switch is doing the opposite. So, when the clock at the gate of the effective switch rises, the clock at the gate of the dummy switch falls, and vice-versa.

Since both terminals of the dummy switch are connected to a certain node in the circuit, while the effective switch only has one, the dummy transistors are usually half the size of the switch transistor. That way, the total coupling capacitance is the same for both transistors.