Source: http://onmyphd.com/?p=si.errors

The switched-current technique is used to sample and hold analog values. This technique has some sources of errors that reduce its accuracy. In this topic, we will talk about some of them.

During sampling, $V_{GS} = V_{DS}$ because the memory transistor is diode-connected. During hold, the drain voltage will probably change which will cause a change in current by two reasons.

a) As you know, MOSFET transistors have a finite output conductance, which means that the drain-source voltage has some influence on the drain current. This can be modeled by a conductance
$$g_{ds} = \frac{\partial I_{DS}}{\partial V_{DS}} = \lambda I_{DS}.$$
b) In a switched-current configuration the gate is floating, and when the drain voltage changes, part of the signal is injected to the gate by $C_{gd}$.

The amount of signal being injected is defined by the capacitive divider formed by $C_{gs}$ and $C_{gd}$, and then the injected signal influences the transistor's current. $$\partial I_D = g_m \frac{C_{gd}}{C_{gs} + C_{gd}} \partial V_{DS}.$$ a) and b) can be joined and it is like the output conductance in switched-current techniques becomes $$g_{ds}' = \frac{\partial I_D}{\partial V_{DS}} = g_{ds} + \frac{C_{gd}}{C_{gs} + C_{gd}} g_m.$$

Click here to know how this affects the value transfer.
Let's say that we are sampling a current in one cell and transferring the same current to another cell. We are going to evaluate the effect of this error in the current copying. First, since the memories are of the same type, it is reasonable to assume that $g_{m1} = g_{m2} = g_m$ and $g_{o1} = g_{o2} = g_o$. $M_1$ is being biased at a current $J$, thereby developing a voltage $V_{GS}$ at its gate. A small current $i_{in}$ is superimposed on this DC operating point, shifting the gate voltage to $v_{GS_1} = V_{GS} + v_{gs_1} = V_{GS} + i_{in}/(g_m+g_o)$.

During the sample phase, the small-signal current sampled is
$$i_1 = i_{in} - i_{g_{o1}}$$
$$i_1 = i_{in} - v_{ds_1} g_o = i_{in} - v_{gs_1} g_o$$
$$i_1 = i_{in} - \frac{i_{in}}{g_m+g_o} g_o$$
$$i_1 = i_{in} \left( 1 - \frac{g_o}{g_m + g_o} \right) $$
$$i_1 = i_{in} \left( \frac{g_m}{g_m + g_o} \right) $$

If the condition $v_{DS_1} = v_{GS_1}$ was kept during hold, the small-signal current transferred would be $i_1 + i_{g_{o1}} = i_{in}$ and the original current would be restored. However, if $v_{DS_1} = v_{GS_2}$ during the hold phase, the current transferred to the next stage is just $$i_{out} = i_1 + i_{g_{o1}}$$ $$i_{out} = i_{in} \left ( \frac{g_m}{g_m + g_o} \right) + v_{ds_1} g_o$$ $$i_{out} = i_{in} \left ( \frac{g_m}{g_m + g_o} \right) - \frac{i_{out} g_o}{g_m + g_o}$$ $$i_{out} = \frac{i_{in} \frac{g_m}{g_m + g_o} }{1 + \frac{g_o}{g_m + g_o}}$$ $$i_{out} = \frac{i_{in}} { 1 + \frac{2 g_o}{g_m} }$$ So the the signal is reduced by $ (1+ 2g_o/g_m)^{-1}$ due to input-output conductance ratio error.

First, let's consider the settling time without the switched resistance. The transistor resistances and capacitances delay the settling of the gate voltage. The memory must be fast enough to settle down before the sampling period ends. Any current that remained to settle results in error.

The small-signal model of the switched-current memory is shown above, where $C_g$ is the gate-source capacitance and $C_d$ is the drain-source capacitance. To find out the transfer function $H(s) = i(s)/i_{in}(s)$: $$i_{in} = i + v_g sC_g + v_d g_o + v_g sC_d$$ By replacing $v_g = i/g_m$ $$i_{in} = i + i \frac{g_o}{g_m} + i \frac{s(C_g + C_d)}{g_m}$$ $$i_{in} = i \left(1 + \frac{g_o + s(C_g + C_d)}{g_m} \right)$$ $$\frac{i}{i_{in}} = \frac{1}{1 + \frac{g_o}{g_m} + \frac{s(C_g + C_d)}{g_m}}$$ $$\frac{i}{i_{in}} = \frac{{1}\bigg/\left(1 + \frac{g_o}{g_m}\right)}{1 + {\frac{s(C_g + C_d)}{g_m}}\bigg/\left(1 + \frac{g_o}{g_m}\right)}$$ $$\frac{i}{i_{in}} = \frac{\frac{g_m}{g_m + g_o}}{1 + \frac{s(C_g + C_d)}{g_m + g_o}}.$$ It can be seen that $i$ settles to $\frac{g_m}{g_m+g_o}i_{in}$ with time constant $\frac{g_m + g_o}{C_d + C_g}\approx\frac{g_m}{C_d + C_g}$.

The switch resistance delays even more the settling of the gate voltage.

The small-signal model of the switched-current memory is shown above, where $g_s$ is the conductance of the switch, $C_g$ is the gate-source capacitance and $C_d$ is the drain-source capacitance. The gate-drain capacitance $C_{gd}$ is negligible in this case because of $g_s$. To find out the transfer function $H(s) = i(s)/i_{in}(s)$: $$i_{in} = i + v_g sC_g + v_d g_o + v_d sC_d$$ To take $v_d$ out of the equation, we note that: $$v_g sC_g = (v_d - v_g) g_s$$ $$v_d = \frac{sC_g + g_s}{g_s}v_g$$ Then $$i_{in} = i + v_g sC_g + \frac{sC_g + g_s}{g_s}v_g ( g_o + sC_d)$$ By replacing $v_g = i/g_m$ $$i_{in} = i + i \frac{sC_g}{g_m} + \frac{sC_g + g_s}{g_s g_m} i ( g_o + sC_d)$$ $$i_{in} = i \left(1 + s\frac{C_g}{g_m} + \frac{sC_g + g_s}{g_s g_m} g_o + \frac{sC_g + g_s}{g_s g_m} sC_d \right)$$ $$i_{in} = i \left(1 + \frac{g_o}{g_m} + s \left(\frac{C_g}{g_m} \left( 1+\frac{g_o}{g_s}\right) + \frac{C_d}{g_m} \right) + s^2\frac{C_d C_g}{g_s g_m} \right)$$ Just to make it more simple, lets assume that $g_o \ll g_m$ and $g_o \ll g_s$. Then $$H(s) = \frac{i}{i_{in}} = \frac{1}{ 1 + s \frac{C_g + C_d}{g_m} + s^2\frac{C_d C_g}{g_s g_m}}$$ This is a second-order low-pass filter with natural frequency $$\omega_o = \sqrt{\frac{g_m g_s}{C_g C_d}}$$ and Q-factor $$Q = \frac{\sqrt{\frac{g_m}{g_s}C_g C_d}}{C_g C_d}$$ As the switch conductance decreases, the memory gets slower and may even become underdamped ($Q > 0.5$) and have ringing, but usually $g_s$ is high enough that it does not reach that point.

When the gate voltage of the switch transistor $M_s$ falls down, the switch turns off. During the turn off, charge is transferred from/to $C_{gs_1}$ by two mechanisms:

a) the charge in the channel of $M_s$ is transferred to the terminals of the switch. Some goes to the drain, some goes to the source.

b) the capacitive coupling of $C_{gs_s}$ and $C_{gs_1}$ transfers charge from the gate of $M_1$ to the gate of $M_s$.

Lets take a look in more detail at what happens during switch turn-off. While $V_{GS_s}$ is above the threshold voltage $V_{TH}$ of $M_s$, the switch is still turned on and the circuit can be depicted as the left figure below.

Both $C_{gs_s}$ and $C_{gd_s}$ have the same value ($=WLC_{ox}/2+WC_{ov}$) because the MOS switch is in triode. While $V_{GS_S}$ is falling, two transient currents flow into the gate of $M_s$
$$i_d = i_s = \frac{\partial V_{GS_s}}{\partial t}\left(WLC_{ox}/2 + WC_{ov}\right).$$
That current removes charge from $C_{gs_1}$, causing the current drawn by $M_1$ to reduce. To compensate this reduction, the difference between $i_{in}$ and ${i_1}$ is again used to charge $C_{gs_1}$, effectively creating a negative feedback loop. However, the loop is not fast enough and only partially compensates.
When the switch turns off (right figure), $g_s$ tends to 0 and there is no more channel of $M_s$. $C_{gs_s}$ and $C_{ds_s}$ become just $WC_{ov}$. The gate of $M_1$ is now floating and the charge is transferred uniquely by capacitive coupling
$$i_d = i_s = \frac{\partial V_{GS_s}}{\partial t}WC_{ov}.$$
The total charge $q$ removed from $C_{gs_1}$ is the integral of $i_s$. That influences the original current by $\partial i = -g_m q /C_{gs_1}$.
It should be noted that the following things influence $\partial i$:

- The
**rate $\frac{\partial V_{GS_s}}{\partial t}$ has a linear influence on the charge removed**. Not only a fast switch off prevents the charge from the channel from being transferred to the terminals, it also affects the effect of the feedback loop described above. - The voltage $V_{GS_1}$ influences when the switch turns off, making the
**charge injection signal dependent**. Not only it determines when the capacitances change value, but also when the charge in the channel stops being transferred to the terminals.

The noise in the switched-current configuration is dominated by thermal and flicker noises. In the figure below, $M_2$ represents all transistors that are supplying current, $M_1$ is the memory transistor and $g_s$ is the conductance of the switch. Current source ending with (t) represent thermal noise, while voltage sources ending with (f) represent flicker noise.

The MOS switch is working on the linear region, therefore it has a homogeneous resistance and its thermal noise is $$v_{ns(t)}^2 = \frac{4kT}{g_s}\Delta f.$$ Both $M_1$ and $M_2$ are in saturation and their thermal noise is $$i_{n(t)}^2 = \frac{8kTg_{m1}}{3}\Delta f$$ $$i_{n2(t)}^2 = \frac{8kTg_{m2}}{3}\Delta f.$$ There is no flicker noise in the switch (it is not flowing any DC current), but both $M_1$ and $M_2$ have the following flicker noises $$v_{n(f)}^2 = \frac{K_f}{W_1L_1C_{ox}|f|}\Delta f$$ $$v_{n2(f)}^2 = \frac{K_f}{W_2L_2C_{ox}|f|}\Delta f$$ The flicker voltages can be converted to currents by the transconductance of each transistor $$i_{n(f)}^2 = g_{m1}^2v_{n(f)}^2 = g_{m1}^2\frac{K_f}{W_1L_1C_{ox}|f|}\Delta f$$ $$i_{n2(f)}^2 = g_{m2}^2v_{n2(f)}^2 = g_{m2}^2\frac{K_f}{W_2L_2C_{ox}|f|}\Delta f$$ The switch thermal noise is much smaller compared to the other noises and can be neglected. Since each noise source is uncorrelated, the total noise power is now the sum of each individual power $$i_N^2 = i_{n(f)}^2 + i_{n2(f)}^2 + i_{n2(t)}^2 + i_{n(t)}^2$$ $$i_N^2 = \left(\frac{K_f}{|f|}\left(\frac{g_{m1}^2}{W_1L_1C_{ox}} + \frac{g_{m2}^2}{W_2L_2C_{ox}}\right) + \frac{8kT}{3}(g_{m1} + g_{m2})\right)\Delta f$$ The noise model during sampling simplifies to

The noise will be filtered by the low-pass filter created by the bandwidth of the circuit. From above, the bandwidth is around: $$\omega_o = \frac{g_m + g_o}{C_g + C_d}.$$ For the simple case of a first-order low-pass filter, the Equivalent Noise Bandwidth is $$\frac{\pi}{2}\omega_o = \frac{\pi}{2}\frac{g_m + g_o}{C_g + C_d}.$$

However, in sampled systems, any signal lying in any frequency above half the sampling frequency (Nyquist frequency) gets replicated back to the base band. So, in simple terms, most of the noise power gets concentrated in the base band frequency.