Source: http://onmyphd.com/?p=slew.rate

- Voltage-current relation for a capacitor
- CMOS transistor model (for the Opamp example)
- Operation of an Opamp at transistor level (for the Opamp example)

Slew rate is the maximum voltage change per unit time in a node of a circuit, due to limited current sink or source. The SR of a circuit is limited by its slowest node, i.e., the one with the smallest Slew rate. Imagine a node in a circuit where the load is capacitive-dominant, i.e., the load is mostly made of a capacitance $C$ (although there is always some very large parallel resistance $R$).

For simplicity let's assume the parallel resistance is infinite, so that all current $I$ entering the load will flow to the capacitor and none to the resistance. Then, the rate of voltage change across the capacitor is defined by the well-known formula: $$\frac{dV}{dt}=\frac{I}{C}.$$ If the current being sourced to this load is limited (and in reality always is), say at $I_{max}$, the maximum voltage change per unit time is: $$SR=\max\left(\frac{dV}{dt}\right)=\frac{I_{max}}{C}$$ This is the Slew-Rate. If the current is being drawn from the capacitor, i.e., the capacitor is discharging, the same rule applies, except the voltage change is negative (negative SR).

Now let's look at some examples of how to calculate the Slew rate.

If you want to avoid distortion of an input signal, you must design a circuit so that every node has a Slew-Rate higher than the highest slope of the input signal. Imagine that the highest sinusoidal you will get as input has frequency $f$. The sinusoide will vary with time $t$ like: $$v(t)=A\sin\left(2\pi ft\right),$$ where $A$ is the amplitude of the sinusoid. The slope of the sinusoid is the derivative: $$\frac{dv(t)}{dt}=A2\pi f\cos(2\pi ft)$$ The highest slope is when the cosine is 1, therefore $SR=\max\frac{dv(t)}{dt}>A2\pi f$. If the circuit amplifies the sinusoide by gain $G$, we must scale the SR by $G$ too.

The slider below controls the slew-rate of a hypothetical node where this sinusoidal signal is being driven. In the above plot you can see the original sine wave $v(t)$ and the slew-rate limited $vsr(t)$ version. As you increase the SR, the distortion is reduced because the SR gets closer to the highest slope of the signal. The highest slope of the signal is $A2\pi f$, with $A=1V$ and $f=2Hz$

SR = V/sOne common characteristic of an opamp is the Slew-Rate. It tells how fast the opamp can charge a capacitor at its ouput and its a measure of its driving power. That, of course, depends on the value of the capacitive load and its ability to provide current. SR in the circuit perspective has already been described above. Now we will look at the transistor level. If you are interested in this example and you need to review the necessary equations, read this topic.

Let's look at the two most ordinary stages of the opamp: the differential pair and the output stage. The analysis of Slew-Rate is a large-signal analysis, therefore we will consider large swings of the input signal. In particular, we will assume that the input differential voltage $v_{d}=v_{+}-v_{-}$ is high enough to let all internal nodes hit the rails (voltage supply for driving PMOS and ground for driving NMOS). It is common that the second stage has a compensation capacitor $C_{C}$ for stability purposes. If it does not have, think of $C_{C}$ as the parasitic capacitors of the PMOS transistor.

- First situation:
$$v_{d}=V_{DD}-V_{SS}.$$
- Second situation:
$$v_{d}=V_{SS}-V_{DD}.$$

$v_{d}$ | $\frac{dv_{1}}{dt}$ | $\frac{dv_{OUT}}{dt}$ |
---|---|---|

$V_{DD}-V_{SS}$ | $-\frac{I_{T}}{C_{C}}$ | $\frac{I_{M_{p}}-I_{M_{n}}}{C_{C}+C}$ |

$V_{SS}-V_{DD}$ | $\frac{I_{T}}{C_{C}}$ | $-\frac{I_{M_{n}}}{C_{C}+C}$ |

Opamp datasheets usually have the SR parameter at the end of the electrical characteristics. They normally refer the conditions used for the numbers they present, or even the testing circuit, although some not even mention the load capacitance (then we assume it is without load).

Here is an example of the LM741 datasheet.