Low DropOut (LDO) Voltage regulators

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A specific class of linear regulators work with a small difference between input and output voltages. These regulators allow the pass transistor to work in a region where they work as a low-value resistance.

What is the dropout voltage?

Dropout voltage is the lowest voltage drop between input and output voltages that still can guarantee the desired output voltage. If the dropout voltage of a regulator is 1V and we need an output voltage of 5V, the input voltage should always be higher than 6V, or else the output voltage will drop below 5V.

What is the difference between a normal and low dropout regulator?

There is a subclass of linear regulators that have a low dropout voltage and, guess what, they are called Low DropOut (LDO) regulators. There are three important aspects that differentiate LDO regulators from normal ones:

• Resistance region: Standard series regulators operate the pass transistor in a region of operation where there is a neglible dependence between the differential input-output voltage and the current flowing through it. This is a desirable property, as a change in the input voltage will have a small impact in the load current and therefore in the output voltage. However, this region of operation requires a minimum voltage drop on the pass transistor (the regions are active region for BJTs and saturation region for MOSFETs). LDO regulators push the transistors to a region where they start to behave as a resistance (saturation for BJTs and linear/triode region for MOSFETs), thereby allowing a smaller dropout voltage.
• Size of pass transistor: Transistors with larger size will have smaller on resistance and therefore a smaller dropout voltage.
• Type of pass element: As will be discussed in the next section, there are various combinations of transistors to create pass elements. The simplest ones (with less transistors) are more suited to LDO regulators because their combined dropout voltage is smaller.

What types of pass elements are there and which ones are suitable for low dropout regulators?

The type of pass element affects the dropout voltage and the quiescent current (the current consumed by the regulator that does not go to the load). Bipolar transistors have a base current which leads to a higher quiescent current compared to MOS transistors. However, MOSFETs require a higher voltage supply than BJTs for the same driving current. Furthermore, some configurations exchange dropout voltage by quiescent curent, such as the Darlington configuration. Now seems a good time to dismistify something: although you see a single NPN BJTs as a pass element in the most basic schematics of linear regulators, in practice other configurations are used. The NPN BJT (or a NMOS FET) requires that the base/gate voltage be higher than the output voltage. If the input voltage is close to the output voltage, it can even happen the base/gate voltage be higher than the input voltage. This, of course, is a pain to do, since the input has the higher voltage you can get. Instead, if a p-type device is used, the base/gate voltage is always lower than the input voltage, which is much easier to handle.

PNP

A PNP transistor is the most basic form of a pass transistor, with the smallest dropout voltage. Hence, they are used for LDO regulators. The dropout voltage is: $$V_{do} = V_{EC}$$ and the quiescent current is: $$I_q = I_B = \frac{I_C}{\beta} = \frac{I_L}{\beta}$$ where $\beta$ is the current gain of the transistor. Given that the load is at the collector, which as a high impedance, the regulator is less stable and more difficult to control.

NPN+PNP

This configuration is a good balance between dropout voltage and quiescent current. The dropout voltage is: $$V_{do} = V_{BE_1} + V_{EC_2}$$ and the quiescent current is: $$I_q = I_{B_2} = \frac{I_{E_1}}{\beta_1\beta_2} = \frac{I_L}{\beta_1\beta_2}$$

Darlington NPN

The Darlington is the configuration that occupies less area (each transistor can be small, since there are three gain stages), but with the largest dropout voltage: $$V_{do} = V_{BE_1} + V_{BE_2} + V_{EC_3}$$ and the smallest quiescent current: $$I_q = \frac{I_L}{\beta_1\beta_2\beta_3}$$ Given the low-voltages used in today's electronics, this configuration is being used less often.

PMOS

The PMOS transistor has negligible quiescent current and the only dropout voltage is its source-drain saturation voltage. Therefore, these are used in LDO regulators. As in the case of the PNP transistor, the load is connected to a high-impedance node (the drain) and the regulator is less stable.

PMOS+NMOS

This composite has a dropout voltage of: $$V_{do} = V_{GS_1} + V_{SD_2}$$ and also has negligible quiescent current.